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Model Release Chip/Chipset (PPxTMU)6 Fab nm Интерфейс Core clock max (MHz) Fillrate7Pix/Tex (MT) Memory Features Datasheets/Documents
Memory max (MB) Memory clock max (MHz) Bus type Bus width (bit)8
Voodoo Graphics Aug-Oct 1996 SST-1 chipset (1x1) [500-0004-02 TMU, 500-0003-03 FBI] 350 PCI 50-57 50-57/50-57 4/6/8 50-57 EDO 64x2 no 2D, PassThrow cable SST-1 Spec
ICS5342 RAMDAC
TVP3409 RAMDAC
Voodoo Rush Aug-Oct 1997 SST-96 chipset (1x1) + 2D Chip;
[500-0004-02 TMU, 500-0005-04 FJR]
350 PCI 75 75/75 6/8 75 EDO 64x2 Alliance AT25 /
MXIC MX86251
2D chip
SST-96 Spec
MX86251 Spec
Voodoo 2 Nov97-Mar98 SST-2 chipset (1x2)
[2x 500-0010-01 BE, 500-0009-01 CK]
350 PCI 90-92 90-92/180-184 8/12 90-92 EDO 64x3 no 2D, PassThrow cable SST-2 Spec
ICS5342 RAMDAC
TVP3409 RAMDAC
Voodoo Banshee Jun-Sep 1998 Single-Chip (1x1)
[500-0013-03 BAN T] (2D/3D)
350 AGP 1x
/PCI
100 100/100 8/16 110 SDR/SGR 128 First single chip 3dfx chipset Banshee Spec
Voodoo 3 1000 Nov98-Apr99 Avenger core (1x2);
[355-0025-001]
250 AGP 2x 125 125/250 8 125 SGR 128 Avenger Spec
Avenger Databook
Voodoo 3 2000 Nov98-Apr99 Avenger core (1x2) 250 AGP 2x
/PCI
143 143/286 16 143 SDR/SGR 128 Avenger Spec
Avenger Databook
Voodoo 3 3000 Nov98-Apr99 Avenger core (1x2) 250 AGP 2x
/PCI
166 166/333 16 166 SDR/SGR 128 Avenger Spec
Avenger Databook
Voodoo 3 3500 July 1999 Avenger core (1x2), A/V processor 250 AGP 2x 183 183/366 16 183 SDR/SGR 128 TV-Tuner Avenger Spec
Avenger Databook
Velocity 100 July 1999 Avenger core (1x1), 1 Software Disabled TMU. 250 AGP 2x 143 143/143 8 143 SGR 128 Second TMU may be Enabled Avenger Spec
Avenger Databook
Velocity 200 Not released Avenger core (1x1), 1 Software Disabled TMU. 250 AGP 2x 143 143/143 16 143 SGR 128 Second TMU may be Enabled Avenger Spec
Avenger Databook
Voodoo 4 45005 Nov99-Sep00 1 x VSA-100(Napalm) (2x1) 250 AGP 4x
/PCI
166 333/333 32 166 SDR 128 Napalm Spec
Napalm Databook
VSA Presentation
Voodoo 4 4800 Not released 1 x VSA-100(Napalm) (2x1) 250 AGP 4x
/PCI
166 333/333 64 166 SDR 128 Napalm Spec
Napalm Databook
VSA Presentation
Voodoo 5 5000 Not released 2 x VSA-100(Napalm) (2x1) 250 AGP 2x
/PCI
166 667/667 321 166 SDR 128x2 Napalm Spec
Napalm Databook
VSA Presentation
Voodoo 5 55005 Nov99-Jun00 2 x VSA-100(Napalm) (2x1) 250 AGP 2x
/PCI
166 667/667 642 166 SDR 128x2 Napalm Spec
Napalm Databook
VSA Presentation
Voodoo 5 60004 Not released 4 x VSA-100(Napalm) (2x1) 250 AGP 2x
/PCI
166-183 1333-1464/1333-1464 1283 166-183 SDR 128x4 Some Revisions have external PSU Napalm Spec
Napalm Databook
VSA Presentation
Voodoo 4-2 4200 Not released 1 x VSA-101(Daytona) (2x1) 180 AGP 4x
/PCI
183 366/366 32 183 DDR 64
Spectre 1000 Not released 1 x Rampage (4x1) 180 AGP 4x 200-250 800-1000/800-1000 64 200-250 DDR 128 20 chips & 4 or 5 worked boards
Spectre 2000 Not released 1 x Rampage (4x1) + 1 x Sage T&L-Chip 180 AGP 4x 200-250 800-1000/800-1000 64 200-250 DDR 128 Sage was not ready
Spectre 3000 Not released 2 x Rampage (4x1) + 1 x Sage T&L-Chip 180 AGP 4x 200-250 1600-2000/1600-2000 128 200-250 DDR 128 Sage was not ready
Model Release Chip/Chipset (PPxTMU)6 Fab nm Интерфейс Core clock max (MHz) Fillrate7Pix/Tex (MT) Memory Features Datasheets/Documents
Memory max (MB) Memory clock max (MHz) Bus type Bus width (bit)8

Notes:

  • 1 Shared by two processors; effectively 16 MB RAM.
  • 2 Shared by two processors; effectively 32 MB RAM.
  • 3 Shared by four processors; effectively 32 MB RAM.
  • 4 The Voodoo 5 6000 was originally intended to have a core and memory clock of 183 MHz, but 3dfx reduced the clock speed to 166 MHz in an attempt to get the boards stable while operating in 2/4/8x AA modes. Since the instability problem was due to a design flaw in the PCB the reduction in clockspeed did nothing in regards to the problem. 3400 and 3700 boards with the "PCI bus modification" by ex-3dfx engineer H.S. run stable in all modes with speeds upwards of 190 MHz.
  • 5 Macintosh versions were released later with the same specs, but only in PCI.
  • 6 Pixel pipeline/s x Texture management unit/s (TMU).
  • 7 Fillrate is measured in Megapixels/sec for pixel fillrate and Megatexels/sec for texture fillrate. Taking advantage of double texture fillrate per clock cycle requires the game engine to make use of multitexturing.
  • 8 Voodoo boards with multiple chips often have independent memory busses for each chip's memory bank. This resulted in boards with large amounts of memory, but the memory was split between the completely separate chips. So while a Voodoo2 has 8 or 12 MB of RAM, this RAM is split up between the texture and framebuffer.
In the case of Voodoo2 12 MiB, there is 4 MB texture RAM for each texture processor and 4 MiB for the framebuffer. When a game is not multitexturing, a total of 8 MiB texture memory is available. With multitexturing, this is halved to 4 MiB. SLI, however, does not double the available RAM because the boards separately calculate their part of the scene.
This split-RAM architecture caused the resolution limits on the older boards. For Voodoo Graphics 4 MB RAM (2 MB framebuffer) framebuffer size only allowed for a 640x480 resolution when z-buffering was used. Some games managed 800x600 without z-buffer, such as MechWarrior 2: 31st Century Combat 3Dfx Edition, Star Wars Jedi Knight: Dark Forces II, and Need for Speed III: Hot Pursuit

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